NXP Delivers World's First No-Offset I2C-Bus Buffers
Unique bus buffers drive I2C-bus signals over long distances, interface with other bus buffers
Eindhoven, Netherlands and San Jose, California, August 23, 2011 — NXP Semiconductors N.V. (NASDAQ: NXPI) today introduced the PCA9525 and PCA9605 — the industry’s first no-offset I2C-bus buffers, which enable system designers to isolate capacitance and interface with other bus buffers. These groundbreaking bus buffers use the no-offset scoreboard method to decide signal direction, rather than using a directional pin and relying on offset voltages to control direction and prevent bus latch-up. Significantly, the no-offset devices are interoperable even with static offset or incremental bus buffers, allowing easy design-in regardless of which other devices are on the bus. In addition, NXP has introduced the PCA9646 — the industry's first fully buffered 4-channel switch with no-offset ports. All devices work to 1 MHz, and the PCA9605 and PCA9646 support Fast-mode Plus (Fm+), which has 10x the normal I2C-bus drive, allowing longer I2C-buses or placement of more devices on the bus.
While I2C buses have traditionally been used in computing, consumer and portable applications where only short bus lengths are needed, the new Fm+ no-offset bus buffers and switch from NXP overcome this limitation by allowing buses to be broken into segments or branches to isolate the bus capacitance into lower capacitive segments meeting I2C-bus specifications. Thus, the PCA9605 and PCA9646 enable I2C-based monitoring and control systems which can serve with hundreds of nodes and/or bus wiring lengths up to 1 km (0.62 miles) at lower frequencies. Designers can now consider running I2C communications over long distances, while using inexpensive commodity cabling such as CAT5 in enterprise computing applications such as servers and mass storage systems, and in industrial and automotive applications. The PCA9525 is useful in standard Fast-mode applications to isolate capacitance.
- The PCA9525 and PCA9605 offer a simple capacitance isolating buffer for 2-wire I2C or SMBus buses, allowing buses to be broken into segments or branches to isolate the bus capacitance into lower capacitive segments with the PCA9605 supporting the higher capacitance limits of Fm+
- While all previous bus buffers have required some sort of offset to allow the device to determine which direction the bus was driving, the new no-offset bus buffers from NXP use the scoreboard method to control direction, and are interoperable with most other bus buffer devices on the I2C bus
- The new no-offset devices from NXP work with I2C-bus (Standard-mode, Fast-mode), SMBus (standard and high power mode), and PMBus; the PCA9605 and PCA9646 also work with I2C Fast-mode Plus (Fm+)
- Fast switching times allow operation in excess of 1 MHz, enabling use of faster peripherals
- Hardware enable input disables the device, allowing bus segments to be disconnected to save power and reuse the same slave addresses over multiple I2C-bus segments
- The no-offset bus buffer inputs follow the I2C-bus specification for Hysteresis which improves bus noise immunity
- Operating voltages from 2.7 V to 5.5 V
- Very low supply current — for example, maximum one microamp in standby, typical 170 microamps operating for the PCA9525
- 4mA pull-down outputs on the PCA9525 and strong 30 mA pull-down outputs on the PCA9605 and PCA9646
- No-offset feature enables designers to mix and match the bus capacitance loading on each side of the device, and also run the bus pull-ups at the appropriate strength
- The scoreboard method requires the SCL to be unidirectional to allow proper operation, which prevents clock stretching or master arbitration across the device